The current market requires that a DDR (Double Data Rate) SDRAM controller have high-speed memory access at a data rate of 533 or 666 MHz. In terms of design, various contrivances for raising speed are in demand.
In a technique of testing a DDR SDRAM controller as well, a test based upon high-speed operation at actual frequencies is essential in order to detect faults, which include delay faults. Mainly, use is made of a loopback test that is not dependent upon the supported frequency region of the tester. In the loopback test of a controller, the memory (DDS SDRAM) is not connected to the controller at the time of the test, data for transmission is returned to the receiving side within the controller and the received data is compared with the expected-value data (the data for transmission), whereby a test at a high-speed transfer rate is implemented without requiring a high-speed tester.
In write access to a DDR SDRAM, a setup spec (tDS) and a hold spec (tDH) have been defined between data (DQ) 1 and a data strobe (DQS) 2, as illustrated in FIG. 12A. Hence there are cases where a phase shift circuit (variable delay circuit) is provided on the side of the controller in order to assure that the phase difference between these will be on the order of 90° of the memory clock period and to supply this to the side of the DDR SDRAM. It should be noted that set-up time is the minimum time in which data must be stabilized prior to the effective edge of the clock (in this case, the rising edge of the data strobe) in a latch circuit, etc. Hold time is the minimum time over which data must be held following the effective edge of the clock.
In read access from a DDR SDRAM, the specifications on the side of the DDR SDRAM are that data 3 and a data strobe 4 are output at the same phase, as illustrated in FIG. 12B. In order to capture data using a 90° phase-shifted signal as the trigger with respect to the data strobe 4 on the controller side, an arrangement in which a phase shift circuit (variable delay circuit) is mounted on the side of the controller generally is adopted (see Patent Document 1).
FIG. 13 illustrates an example of the typical circuit configuration of a DDR SDRAM controller having a loopback test function. The structural elements shown in FIG. 13 will be described below. In FIG. 13, a clock signal (Clock) 5 is an internal clock signal having the same period as that of a clock signal supplied to a memory DDR SDRAM), not shown. A variable delay circuit 6 constituting a phase shift circuit receives the internal clock signal (Clock) 5 as an input, adds a 90°-phase difference to the internal clock signal (Clock) 5 and outputs the resultant signal. Although there is no particular limitation, the variable delay circuit 6 in the DDR SDRAM comprises an MDLL (Master Delay Lock Loop) and an SDLL (Slave Delay Lock Loop). The MDLL discriminates the amount of delay from the degree of a shift, which is indicated by a phase shift amount signal [OFFSET (W)] 7 that is output from a normal-mode phase shift amount control circuit 23, and generates a delay-changeover control signal corresponding to the period of the internal clock signal (Clock) 5. In accordance with the delay-changeover control signal from the MDLL, the SDLL adds a delay to the internal clock signal 5 and outputs the resultant signal.
The phase shift amount signal 7 is a signal delivered from the normal-mode phase shift amount control circuit 23 to the variable delay circuit 6 in order to set the amount of phase shift of the variable delay circuit 6 when the normal mode (ordinary operating mode) is in effect.
The normal-mode phase shift amount control circuit 23 includes a register (not shown) which, when the normal mode is in effect, is capable of being set to a fixed value indicating 90° or to a value from a host system (not shown). The register (not shown) holds the shift degree at the time of the normal mode and is capable of being set from a host apparatus such as a CPU (not shown) by software or is set from an external circuit such as a calibration circuit (not shown) that derives the optimum degree of shift.
A selector 8, which receives as inputs the delayed output of the variable delay circuit 6 and a signal having a phase difference of 180° with respect to the internal clock signal 5, bypasses the variable delay circuit 6 (selects the signal having the phase difference of 180° with respect to the internal clock signal 5) and makes the phases of output of the data signal and output of the data strobe signal the same when the circuit on the input side is tested. That is, the selector 8 selects the output from the variable delay circuit 6 when the normal mode is in effect and selects a signal having a phase difference of 180° with respect to the internal clock signal 5 when the circuit on the input side is subjected to a loopback test. In order to generate a signal having a phase difference of 180° with respect to the internal clock signal 5, use is made of a signal that is the result of reversing the polarity of the internal clock signal 5 by an inverter circuit 31, by way of example.
The output of the selector 8 is supplied to a write-data sampling circuit (data output circuit) 10 as a clock signal 9 for data output. The data output circuit 10 includes flip-flops F/F1 and F/F2 for sampling write data in response to the clock signal. The flip-flops F/F1 and F/F2 respectively sample write data (POS) and write data (NEG) at the rising and falling edges of the clock signal 9 for data output. The outputs of the flip-flops F/F1 and F/F2 are multiplexed by a multiplexer (selector) 10-1, and the write-data signal which undergoes a double-rate conversion is output. That is, two items of write data are output in one clock cycle. When the clock signal 9 for data output is HIGH and LOW, the multiplexer 10-1 selects and outputs the outputs of the flip-flops F/F1 and F/F2, respectively. It should be noted that the write data (POS) and write data (NEG) represent write data sampled at the positive-going (rising) edge and negative-going (falling) edge of the clock signal 9 for data output, respectively, in the flip-flops F/F1 and F/F2.
A bi-directional interface buffer 11 has an output buffer 11-1 for outputting a data signal and an input buffer 11-2 for inputting a data signal. The output buffer 11-1 outputs the signal from the data output circuit 10 to a DQ external terminal 13 serving as a data input/output terminal. The input buffer 11-2 receives a signal from the DQ external terminal 13. In the normal mode, the output buffer 11-1 is set to a high-impedance state (off) at the time of data input.
A buffer 12 is a bi-directional interface buffer for receiving and outputting the data strobe signal DQS. The buffer 12 has an output buffer 12-1 for outputting the data strobe signal and an input buffer 12-2 for receiving the data strobe signal.
With regard to output of the data strobe signal, a signal having a phase difference of 180° with respect to the internal clock signal 5 is output. In order to generate a signal having a phase difference of 180° with respect to the internal clock signal 5, use is made of a signal that is the result of reversing the polarity of the internal clock signal (Clock) 5 by an inverter circuit 32, by way of example.
The DQ external terminal 13 is connected to the bi-directional interface buffer 11.
A DQS external terminal 14 serving as a data strobe input/output terminal is connected to the bi-directional interface buffer 12. Ordinarily, a single data strobe (DQS) is required per 8-bit data (DQ [7:0]).
The circuit on the input side has a variable delay circuit 15 for applying a phase shift with respect to the data strobe signal input from the buffer 12.
The variable delay circuit 15 comprises an MDLL (Master Delay Lock Loop) for generating a delay-changeover control signal, which corresponds to the period of the internal clock, from the shift degree indicated by a phase-shift-amount signal 16 that is supplied from a normal-mode phase-shift-amount control circuit 24, and an SDLL (Slave Delay Lock Loop) which, in accordance with the delay-changeover control signal from the MDLL, adds on a delay to the data strobe signal that enters via the bi-directional interface buffer 12 and outputs the resultant signal.
The phase-shift-amount signal 16 is a signal delivered from the normal-mode phase shift amount control circuit 24 to the variable delay circuit 15 in order to set the amount of phase shift of the variable delay circuit 15 when the normal mode is in effect.
The normal-mode phase shift amount control circuit 24 includes a register (not shown) which, when the normal mode is in effect, is set to a fixed value indicating 90° or is capable of being set from a host system (not shown). The register holds the shift degree at the time of the normal mode and is capable of being set from a host apparatus such as a CPU (not shown) by software or is set from an external circuit such as a calibration circuit (not shown) that derives the optimum degree of shift.
A selector 17, which receives as inputs the output of the variable delay circuit 15 and the output signal from the input buffer 12-2 of interface buffer 12, bypasses the variable delay circuit 15 when the circuit on the output side is tested. That is, the selector 17 selects the output from the variable delay circuit 15 when the normal mode is in effect and selects the output signal from the input buffer 12-2 of the bi-directional interface buffer 12 when the circuit on the output side is subjected to a loopback test.
A signal 18 is a read-data capture clock signal selected by the selector 17. A read-data capture circuit (input-data sampling circuit) 19 includes flip-flops F/F3 and F/F4 for sampling read data, which is the input signal from the input buffer 11-2. The flip-flops F/F3 and F/F4 sample the read data in synchronization with the positive-going and negative-going edges of the read-data capture clock signal 18. It should be noted that there are also cases where the read-data capture circuit 19 has a FIFO (First In, First Out) configuration.
Write data 20 of an output source is data which is for being written to memory and is supplied from internal logic (not shown) when the normal mode is in effect. The write data 20 is supplied from a pattern generating circuit (an internal circuit), not shown when the loopback test is conducted.
Read data 21 is read data sampled by the read-data capture circuit 19. Read data (POS) and read data (NEG) represent read data sampled respectively at the positive-going (rising) edge and negative-going (falling edge) of the read-data capture clock signal 18 by the flip-flops F/F3, F/F4 in the read-data capture circuit 19.
A comparator circuit A (22) compares the output-source write data 20 (expected value) with the read data 21 captured by loopback (i.e., the comparator performs an expected-value comparison).
<Memory Access Operation>
In a case where write access to a memory (DDR SDRAM) (not shown) is performed in the DDR SDRAM controller having a loopback test function according to the prior art of FIG. 13, a signal phase-shifted by 90° with respect to the internal clock signal 5 by the variable delay circuit 6 is selected by the selector 8, the output-source write data 20 is converted to a signal having a double data rate by the data output circuit 10 in accordance with the clock signal 9 for data output of the selected signal, and the resultant signal is output to the data terminal 13 via the interface buffer 11, whence the signal is sent to the memory (not shown) side.
Further, a signal that is 180° out of phase with the internal clock signal 5 is output to the data strobe terminal 14 via the output buffer 12-1 of the interface buffer 12, whence the signal is sent to the memory (not shown) side.
On the other hand, in a case where read access from memory (not shown) is carried out, read data that has entered from the data terminal 13 is captured by the read-data capture circuit 19 via the input buffer 11-2 of the interface buffer 11. As for the read-data capture clock signal 18, a signal phase-shifted by 90° with respect to the data strobe signal (which is output from the DDR SDRAM), which enters from the DQS external terminal 14 via the buffer 12-2 of the interface buffer 12, by the variable delay circuit 15 is selected by the selector 17 and used.
<Loopback Test Technique>
At the time of the loopback test, the memory (DDR SDRAM) (not shown) is not connected to the controller and the data signal and data strobe signal, which have been output from the output buffers 11-1 and 12-1, respectively are loop backed and received by the corresponding input buffers 11-2 and 12-2, respectively, and testing of a path of the data and data strobe of the output-side circuit and input-side circuit in the controller is conducted in a manner described later.
However, in a case where the loopback test is conducted, if use is made of the signals phase-shifted by the variable delay circuits 6 and 15 of both the output-side and input-side circuits in a manner similar to that when memory access is performed, there is contention between timing of the changeover of the data and timing of the clock, and normal data capture cannot be carried out. This will be described with reference to FIG. 14. FIG. 14 is a timing waveform diagram illustrating loopback operation in a case where the variable delay circuits 6, 15 of both the output-side and input-side circuits are not bypassed. In FIG. 14, data 123, which has been imparted with a phase difference of 90° by the variable delay circuit 6 on the output side, and a data strobe 124 are output to the DQ external terminal 13 and DQS external terminal 14, respectively. However, the data strobe signal that has been looped back and input is shifted in phase by 90° in the variable delay circuit 15 on the input-side circuit. In the read-data capture circuit 19, therefore, the changeover of input data 125 and the transition edge of input clock 126 occur at the same timing (see the arrows A in FIG. 14). That is, the data changeover (Data0 to Data 1, Data2 to Data3) and the rising edge of input clock signal 126 of the read-data capture flip-flop F/F3 occur at the same timing. Similarly, data changeover (Data1 to Data 2) and the falling edge of input clock signal occur at the same timing. In the flip-flops F/F3 and F/F4 of the read-data capture circuit 19 in FIG. 13, contention with clock timing occurs and normal capture of data cannot be performed.
With the conventional loopback test method, therefore, the circuit on the output side and the circuit on the input side are tested separately. That is, when the output-side circuit is tested in FIG. 13, the selector 17 bypasses the variable delay circuit 15, and when the input-side circuit is tested, the selector 8 bypasses the variable delay circuit 6. Testing of the output-side circuit and testing of the input-side circuit will be described below.
<Testing of Output-Side Circuit>
FIG. 15 is a diagram illustrating timing waveforms when the output-side circuit is tested in the arrangement of FIG. 13. In a case where the output-side circuit is tested, a phase difference of 90° is furnished between data 127 and a data strobe 128 by the variable delay circuit 6 of the output-side circuit in a manner the same as that of the normal (normal-mode) memory-write access operation. The data 127 and data strobe 128 that have been output are looped back at the DQ external terminal 13 and DQS external terminal 14 and captured in the controller. Since the entered data 127 and data strobe 128 already have the phase difference of 90° between them, the selector 17 selects the output of the input buffer 12-2 and not the output of the variable delay circuit 15. The clock signal that has bypassed the variable delay circuit 15 is selected by the selector 17 as a clock 129 of the read-data capture circuit 19, whereby normal data capture is carried out. The flip-flop F/F3 of the read-data capture circuit 19 samples the input data (Data0, Data2) at the rising edge of the clock 129, and the flip-flop F/F4 samples the input data (Data1, Data3) at the falling edge of the clock 129.
In FIG. 13, the test of the output-side circuit is conducted by comparing the value of the output-source write data 20 and the value of the read data 21 sampled by the input-data capture circuit 19 using the comparator circuit A (22) and then confirming coincidence. At this time the read data (POS) and write data (POS) corresponding to the expected value thereof are compared, and the read data (NEG) and write data (NEG) corresponding to the expected value thereof are compared.
<Testing of Input-Side Circuit>
FIG. 16 is a diagram illustrating timing waveforms when the input-side circuit is tested in the arrangement of FIG. 13. In a case where the input-side circuit is tested, no phase difference is furnished between data 130 and a data strobe 131 at the DQ external terminal 13 and DQS external terminal 14 in a manner the same as that of the normal (normal-mode) memory-read access operation. In the output-side circuit, therefore, the selector 8 bypasses the variable delay circuit 6.
The data 130 and data strobe 131 that have been output from the DQ external terminal 13 and DQS external terminal 14, respectively, are looped back at the DQ external terminal 13 and DQS external terminal 14 and these are captured in the input-side circuit within the controller while the phase between the data 130 and data strobe 131 is kept the same.
In the input-side circuit, a signal (132 in FIG. 16) phase-shifted by 90° by the variable delay circuit 15 is selected by the selector 17 in a manner the same as that of the normal memory-read access operation, and this is used as the clock of the flip-flops F/F3 and F/F4 of the read-data capture circuit 19.
In FIG. 13, the input-side circuit can be tested by comparing the value of the write data 20 and the value of the read data 21 by the comparator circuit A (22) and then confirming coincidence. At this time the read data (POS) and write data (POS) corresponding to the expected value thereof are compared, and the read data (NEG) and write data (NEG) corresponding to the expected value thereof are compared.
By effecting operation at actual speed using the conventional loopback test method described above, it is possible to detect faults inclusive of delay faults in the setting of the 90° phase shift by the variable delay circuits of the output-side and input-side circuits.
However, in the circuit arrangement shown in FIG. 13, the selectors 8 and 17 are inserted in order to bypass the variable delay circuits 6 and 15 at the time of the loopback test. Consequently, the propagation delay time of the selectors 8 and 17 is always added to the clock path not only at the time of the loopback test but also when the normal mode is in effect. The insertion of the selectors leads to an increase in path delay and there are cases where this becomes a burden in assuring timing at the design stage. Further, since delay faults cannot be detected in a case where the amount of phase shift in a variable delay circuit is changed over finely, measurement can only be performed by a costly high-speed tester in order to test the phase changeover function.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2005-78547